(a) Field of the Invention
The present invention relates to a plasma display panel (PDP). More particularly, the present invention relates to a driving circuit of the PDP.
(b) Description of the Related Art
Recently, PDPs have been highlighted among flat display devices due to high brightness, emission efficiency, and wide viewing angle. The PDP is a flat display device for displaying characters or images using plasma caused by gas discharge, and several tens to several millions of pixels are arranged in a matrix format on the PDP according to the PDP size.
FIG. 1 is a partial perspective view of a PDP. FIG. 2 shows an arrangement of electrodes in the PDP. As shown in FIG. 1, the PDP includes two glass substrates 1, 6 which are arranged in a face-to-face relationship. On first substrate 1, pairs of scan electrode 4 and sustain electrode 5, which are covered with dielectric layer 2 and protective layer 3, are arranged in parallel. On second substrate 6, a plurality of address electrodes 8, which are covered with insulating layer 7, are arranged. Barrier ribs 9 are formed in parallel with address electrodes 8 on insulating layer 7. Fluorescent material 10 is formed on the surface of insulating layer 7 and on both sides of barrier ribs 9. Glass substrates 1, 6 are arranged in a face-to-face relationship with discharge space 11 formed therebetween, such that scan electrodes 4 and sustain electrodes 5 lie in a direction perpendicular to address electrodes 8. Discharge space 11 at intersections of address electrodes 8 and the pairs of scan electrode 4 and sustain electrode 5 forms discharge cells 12.
As shown in FIG. 2, the PDP has a pixel matrix in an m×n matrix format. A plurality of address electrodes A1 to Am are arranged in a column direction, and a plurality of scan electrodes Y1 to Yn and a plurality of sustain electrodes X1 to Xn are alternately arranged in a row direction.
Generally, in the PDP one frame is divided into a plurality of subfields, and is driven. Grays of the PDP can be expressed by a combination of the subfields, and generally, each subfield includes a reset period, an address period, and a sustain period. The reset period is a period for erasing wall charges that have been formed by a previous sustain discharge, and setting up a new wall charge in order to stably perform a next address discharge. The address period is a period for selecting cells being turned on and cells being turned off, and accumulating a wall charge on cells being turned on (addressed cell). The sustain period is a period for performing a sustain discharge to display a video image on an addressed cell. Here, “wall charge” means a charge that is formed on a wall close to each electrode of the discharge cell and is accumulated on the electrode. The wall charge is described as being “formed” or “accumulated” on the electrode, although the wall charge does not actually contact the electrodes. Further, “wall voltage” means a potential difference formed on the wall of the discharge cell by the wall charge.
An address operation of the PDP is performed by the operation of a scan IC and an address IC, which include a plurality of selection circuits having two switches connected serially. Further, the output of the scan selection circuit corresponds to the scan electrode (Y electrode) and the output of the address selection circuit corresponds to the address electrode. Generally, one driver IC includes a plurality of selection circuits. However, hereinafter one driver IC is understood to include one selection circuit for convenience.
FIG. 3 shows a connection diagram of a scan IC and a Y electrode according to a conventional circuit. As shown in FIG. 3, the output of SCAN IC 1 is coupled to scan electrode Y1, and the output of SCAN IC2 is coupled to scan electrode Y2.
Because the size of panels has gradually been enlarged in recent years, the requirement for capacity of the circuit elements has also gradually increased. Thus, the capacity of a driver IC (scan IC and address IC) also needs to be increased. In particular, a driver IC that is capable of dealing with a large quantity of current is required, since the driving current for a 70 inch grade PDP is three times greater than the driving current for a 40 inch grade PDP. However, the production amount of the large sized PDP is smaller than that of the 40 inch grade PDP, thus the development of an exclusive driver IC for the large size PDP is not advantageous with regard to cost.